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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A
Selectable-Output DC/DC Converters
Circuits
The circuits shown in Figures 12 through 14 introduce several concepts when
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q1’s drain.
using these Sequencing controls on Point-of-Load (POL) converters. These
circuits are only for reference and are not intended as ?nal designs ready for
your application. Also, numerous connections are omitted for clarity.
Figure 14. Proportional Phasing
Figure 12. Wiring for Simultaneous Phasing
Figure 14 shows both a RC ramp on Master POL A and a proportional track-
Figure 12 shows a basic Master (POL A) and Slave (POL B) connected so
the POL B ramps up identically to POL A as shown in timing diagram, Figure
8. RC network R1 and C1 charge up at a rate set by the R1-C1 time constant,
giving a roughly linear ramp. As POL A reaches 3.3V OUT (the setpoint of POL
B), POL B will stop rising. POL A then continues rising until it reaches 5V. R1
should be signi?cantly smaller than the internal bias current resistor from the
Sequence pin. Start with a 20k ?? value. We assume that the critical phase is
only on power up therefore there is no provision for ramped power down.
Figure 13. Self-Ramping Power Up
Figure 13 shows a single POL and the same RC network. However, we have
added a FET at Q1 as an up/down control. When V IN power is applied to the
POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased
off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate.
Note: Q1’s gate would typically be controlled from some external digital logic.
ing divider (R2 and R3) on POL B. We have also added an optional very small
noise ?lter cap at C2. Figure 14’s circuit corresponds roughly to Figure 9’s
timing for power up.
Guidelines for Sequence/Track Applications
[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.
Normally, you should just leave the On/Off pin open.
[2] Allow the converter to stabilize (typically less than 20 mS after +V IN
power on) before raising the Sequence input. Also, if you wish to have a
ramped power down, leave +V IN powered all during the down ramp. Do
not simply shut off power.
[3] If you do not use the Sequence/Track pin, leave it open or tied to +V IN .
[4] Observe the Output slew rate relative to the Sequence input. A rough
guide is 2 Volts per millisecond maximum slew rate. If you exceed
this slew rate on the Sequence pin, the converter will simply ramp up
at it’s maximum output slew rate (and will not necessarily track the
faster Sequence input). The reason to carefully consider the slew rate
limitation is in case you want two different POL’s to precisely track
each other.
[5] Be aware of the input characteristics of the Sequence pin. The high
input impedance affects the time constant of any small external ramp
capacitor. And the bias current will slowly charge up any external caps
over time if they are not grounded. The internal pull-up resistor to +V IN is
typically 400k ? to 1M ? .
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